The invention relates to an integrated circuit comprising a plurality of cores, with each core being associated a respective core test control block (TCB) for controlling the core in a test mode thereof, each core TCB comprising a core shift register for holding test control data, the core TCBs being serially linked in a chain, each core TCB comprising a first mode for shifting the test control data along the chain and a second mode for applying the test control data to the associated core.
The current trend in IC design is to speed up design time by reusing pre-developed (parameterized) versions of large modules, the so-called cores. Although any such core can have proven to be well-designed by many successful (re-)uses, implementations in silicon have to be tested as production faults always show up. Hereto, the cores that are available to the chip designer are often accompanied by corresponding test schemes that are tailored for the core at hand. Preferably, not only the cores are reused but also their corresponding test schemes. In addition to the cores themselves, also the interconnects between the cores have to be tested.
Both kinds of tests have to be organised on a chip level and possibly be activated and controlled via the chip pins. It is the task of the chip designer to design circuitry herefor. With the number of cores on a chip and their complexity increasing, this task is getting more and more complicated. Furthermore, because the number of available chip pins and the available area are limited, the chip designer has less and less means for performing this task. Specifically, it is a problem how to provide the cores with test control data for controlling the cores during test.
A straightforward approach to that problem is described in U.S. Pat. No. 5,491,666. The known integrated circuit is as described in the preamble. Each core is provided with a core TCB that is essentially a Test Access Port (TAP) controller according to the well known boundary-scan test standard, as defined by IEEE Std. 1149.1. The TAP controllers are linked in a serial chain for serially shifting in the test control data into shift registers. The specification of the TAP controller fits in with such an arrangement, as it prescribes a path between an input node and an output node of the controller via an internal shift register, and a state machine for controlling the shifting in of test control data and the application thereof to the associated core. A problem with such kind of core TCBs is that the state machine is complicated and therefore requires a relatively large area of the integrated circuit. Moreover, a multitude of such core TCBs are required in the integrated circuit.